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1 m e m o r y all data sheets are subject to change without not ice (858) 503-3300 fax: (858) 503-3301 - www.maxwell.com 16-bit, 20 khz a/d converter ?2005 maxwell technologies inc. all rights reserved. 01.17.05 r ev 3 5102alp f eatures : ? monolithic cmos a/d converters - inherent sampling architecture - 2-channel input multiplexer - flexible serial output port conversion time - 5102a: 40 s linearity error: 0.001% fs - guaranteed no missing codes self-calibration maintains accuracy - over time and temperature fully latchup protected d escription : maxwell technologies? 5102alprp is a 16-bit mono- lithic cmos analog-to-digital converter capable of 20 khz throughput. on-chip self-calibration achieves nonlin- earity of 0.001% of fs and guarantees 16-bit no miss- ing codes over the entire specified temperature range. offset and full-scale errors are minimized during the cali- bration cycle, eliminating the need for external trimming. the 5102alp each consist of a 2-channel input multi- plexer, dac, conversion and calibration microcontroller, clock generator, comparator, and serial communications port. the inherent sampling architecture of the device eliminates the need for an external track and hold ampli- fier. maxwell technologies' patented r ad -p ak ? packaging technology incorporates radiation shielding in the micro- circuit package. it eliminates the need for box shielding while improving the tid performance in most space environments. this product is available with screening up to maxwell technologies self-defined class k. clock generator control calibration sram microcontroller 16-bit charge redistribution dac - + - + - + - + comparator clkin xout refbuf vref ain1 ain2 ch1/2 agnd va+ va- dgnd vd- vd+ sclk test sckmod outmod hold sleep rst stby code bp/up crs/fin trk1 trk2 ssh/sdl sdata 144 23 22 +vdig dgnd -vdig rst clki n xout stby dgnd +vdig trk1 trk2 crs/ fi n ssh/ sd l hold ch1/ 2 sclk + lptbi t nc -vdig -vdig dgnd +vdig +van agnd -vanlog -lptv +lptv sd a ta code bp/ up outmod ain1 vref refbu f agnd -vanlog ain2 +vanlog lptstatus sckm od sleep -vanlog agnd +vanlog
m e m o r y 2 01.17.05 r ev 3 all data sheets are subject to change without notice ?2005 maxwell technologies inc. all rights reserved. 5102alp 16-bit, 20 khz a/d converter t able 1. 5102alp a bsolute m aximum r atings (agnd, dgnd = 0v, all voltages with respect to ground ) p arameter s ymbol m in m ax u nit dc power supplies: 1 positive digital negative digital positive analog negative analog 1. in addition, vd+ must not be greater than (va+) 0.3v. vd+ vd- va+ va- -0.3 0.3 -0.3 0.3 6.0 -6.0 6.0 -6.0 v input current, any pin except supplies 2 2. transient currents of up to 100 ma will not cause scr latchup. i in -- 10 ma analog input voltage (ain and v ref pins) v ina (va-) -0.3 (va+) 0.3 v digital input voltage v ind -0.3 (va+) 0.3 v ambient operating temperature t a -15 55 o c storage temperature t stg -65 150 o c t able 2. 5102alp r ecommended o perating c onditions (agnd, dgnd = 0v, all voltages with respect to ground ) p arameter s ymbol m in t yp m ax u nit dc power supplies: positive digital negative digital positive analog negative analog vd+ vd- va+ va- 4.5 -4.5 4.5 -4.5 5.0 -5.0 5.0 -5.0 va+ -5.5 5.5 -5.5 v analog reference voltage vref 2.5 4.5 (va+) -0.5 v analog input voltage 1 unipolar bipolar 1. the 5102alprp can accept input voltage up to the analog supplies (va+ and va-). they will produce an output of all 1s for inputs above v ref and all 0s for inputs below agnd in unipolar mode and -v ref in bipolar mode, with binary coding (code = low). v ain agnd -v ref -- -- v ref v ref v
m e m o r y 3 01.17.05 r ev 3 all data sheets are subject to change without notice ?2005 maxwell technologies inc. all rights reserved. 5102alp 16-bit, 20 khz a/d converter t able 3. a nalog c haracteristics (t a = t min to t max ; va+, vd+ = 5v; va-, vd- = -5v; v ref = 4.5v; f ull -s cale i nput s inewave , 200 h z ; clkin = 1.6 mh z ; f s = 20 k h z ; b ipolar m ode ; frn m ode ; ain1 and ain2 tied together , each channel tested separately ; a nalog s ource i mpedance = 50 w with 1000 p f to agnd unless otherwise specified ) p arameter s ymbol m in t yp m ax u nit accuracy resolution 1 res 16 -- -- bits full scale error 2 drift 3 fse -- -- 1 2 5 -- lsb dlsb unipolar offset 2 drift 3 voff -- -- 1 2 5 -- lsb dlsb bipolar offset 2 drift 3 boff -- -- 2 2 5 -- lsb dlsb bipolar negative full scale error 2 drift 2 bnfse -- -- 2 2 5 -- lsb dlsb integral nonlinearity inl -- -- 3 lsb differential nonlinearity dnl -- 1 -- lsb dynamic performance (bipolar mode) peak harmonic or spurious noise 2, 4 94 100 -- db total harmonic distortion 4 -- 0.002 -- % signal-to-noise ratio 2, 4 0 db input -60 db input 87 -- 90 30 -- -- db noise 5 unipolar mode bipolar mode -- -- 35 70 -- -- vrms analog input aperture time -- 30 -- ns aperture jitter -- 100 -- ps input capacitance 6 , 4 unipolar mode bipolar mode -- -- 335 215 -- -- pf conversion and throughput conversion time 7 t c -- 40.625 -- s acquisition time 8 t a -- 9.375 -- s throughput 9, 10 f tp -- 20 -- khz power supplies
m e m o r y 4 01.17.05 r ev 3 all data sheets are subject to change without notice ?2005 maxwell technologies inc. all rights reserved. 5102alp 16-bit, 20 khz a/d converter power supply current 11 positive analog negative analog (sleep high) positive digital negative digital i a+ i a- i d+ i d- -- -- -- -- 8.5 -7.7 0.5 -0.5 12 -11 1.5 -1.5 ma power consumption 11, 12 (sleep high) (sleep low) p do p ds -- -- 85 45 130 -- mw power supply rejection 13 positive supplies negative supplies psr psr -- -- 84 84 -- -- db 1. minimum resolution for which no missing codes are guaranteed over the specified temperature range. 2. applies after calibration at any temperature within the specified temperature range. 3. total drift over specified temperature range after calibration at power-up at 25c. 4. guaranteed by characterization (5102a die). 5. wideband noise aliased into the baseband. referred to the input. 6. applied only in the track mode. when converting or calibrating, input capacitance will not exceed 30 pf. 7. conversion time scales directly to the master clock speed. the times shown are for synchronous, internal loopback (frn mode). in pdt, rbt, and ssc modes, asynchronrous delay between the falling edge of hold and the start of conversion may add to the apparent conversion time. this delay will not exceed 1 master clock cycle + 140 ns. 8. the 5102alprp requires 6 clock cycles of coarse charge, followed by a minimum of 5.625 s of fine charge. frn mode allows 9 clock cycles for fine charge which provides for the minimum 5.625 s with a 1.6 mhz clock; however, in pdt, rbt, or ssc modes, at clock frequencies less than 1.6 mhz, fine charge may be less than 9 clock cycles. 9. throughput is the sum of the acquisition and conversion times. it will vary in accordance with conditions affecting acquisiti on and conversion times described above. 10.typical value (measured). 11. all outputs unloaded. all inputs at vd+ or dgnd. 12.power consumption in the sleep mode applies with no master clock applied (clkin held high or low). 13.with 300 mv p-p, 1 khz ripple applied to each supply separately in the bipolar mode. rejection improves by 6 db in the unipo - lar mode to 90 db. t able 4. 5102alp s witching c haracteristics (t a = t min to t max ; va+, vd+ = 5v 10%; va-, vd- = -5v 10%; i nputs : l ogic 0 = 0v, l ogic 1 = vd+; c l = 50 p f) p arameter s ymbol m in t yp m ax u nit clkin period 1, 2 t clk 0.5 -- 10 s clkin low time t clkl 200 -- -- ns clkin high time t clkh 200 -- -- ns t able 3. a nalog c haracteristics (t a = t min to t max ; va+, vd+ = 5v; va-, vd- = -5v; v ref = 4.5v; f ull -s cale i nput s inewave , 200 h z ; clkin = 1.6 mh z ; f s = 20 k h z ; b ipolar m ode ; frn m ode ; ain1 and ain2 tied together , each channel tested separately ; a nalog s ource i mpedance = 50 w with 1000 p f to agnd unless otherwise specified ) p arameter s ymbol m in t yp m ax u nit
m e m o r y 5 01.17.05 r ev 3 all data sheets are subject to change without notice ?2005 maxwell technologies inc. all rights reserved. 5102alp 16-bit, 20 khz a/d converter crystal frequency 1, 2 f xtal -- 1.6 -- mhz sleep rising to oscillator stable 3 -- 20 -- ms rst pulse width 4 t rst 150 -- -- ns rst to stby falling t drrs -- 100 -- ns rst rising to stby rising t cal -- 2,882,040 -- tclk ch1/2 edge to trk1, trk2 rising 5 t drsh1 -- 80 -- ns ch1/2 edge to trk1, trk2 falling 5 t dfsh4 -- -- 68t clk + 260 ns hold to ssh falling 6 t dfsh2 -- 60 -- ns hold to trk1, trk2, falling 6 t dfsh1 66t clk -- 68t clk + 260 ns hold to trk1, trk2, ssh rising 6 t drsh -- 120 -- ns hold pulse width 7 t hold 1t clk + 20 -- 63t clk ns hold to ch1/2 edge 6 t dhlri 300 -- 64t clk ns hold falling to clkin falling 7 t hcf 275 -- 1t clk + 10 ns pdt and rbt modes sclk input pulse period t sclk 1000 -- -- ns sclk input pulse width low t sckll 500 -- -- ns sclk input pulse width high t sclkh 500 -- -- ns sclk input falling to sdata valid t dss -- 100 150 ns hold falling to sdata valid - pdt mode t dhs -- 140 230 ns trk1, trk2 falling to sdata valid 8 t dts -- 65 125 ns frn and ssc modes sclk output pulse width low t slkl -- 2t clk -- t clk sclk output pulse width high t slkh -- 2t clk -- t clk sdata valid before rising sclk t ss 2t clk - 100 -- -- ns sdata valid after rising sclk t sh 2t clk - 100 -- -- ns sdl falling to 1st rising sclk t rsclk -- 2t clk -- ns last rising sclk to sdl rising t rsdl -- 2t clk 2t clk + 200 ns hold falling to 1st falling sclk t hfs 6t clk -- 8t clk + 200 ns ch1/2 edge to 1st falling sclk t chfs -- 7t clk -- t clk 1. minimum clkin period is 0.625 s is frn mode (20 khz sample rate). 2. external loading capacitors are required to allow the crystal to oscillate. maximum crystal frequency is 1.6 mhz in frn mode (20 khz sample rate). 3. with a 2.0 mhz crystal, two 33 pf loading capacitors and a 10 mw parallel resistor. 4. guaranteed by initial characterization (5102a die). 5. these times are for frn mode. 6. these times are for pdt and rbt modes. t able 4. 5102alp s witching c haracteristics (t a = t min to t max ; va+, vd+ = 5v 10%; va-, vd- = -5v 10%; i nputs : l ogic 0 = 0v, l ogic 1 = vd+; c l = 50 p f) p arameter s ymbol m in t yp m ax u nit
m e m o r y 6 01.17.05 r ev 3 all data sheets are subject to change without notice ?2005 maxwell technologies inc. all rights reserved. 5102alp 16-bit, 20 khz a/d converter lpt? o peration latchup protection technology (lpt?) automatically detects an increase in the supply current of the 5102alp con- verter due to a single event effect and internally cycle the power to the converter off, then on, which restores the steady state operation of the device. if data outputs are connected to a bus with other bus driver circuits, all external data bus drivers must be tri-stated and individual pull up resistors to the supply voltage (if used on the data bus) must no be less than 10 k ohm typical to assure proper single event effect recovery. status can also be used to generate an input to the system data processor indicating that an lpt? cycle has occurred, and the protected device output accuracy may not be met until after the respective recovery time to the event. the status signal is generated from an advanced cmos logic gate output. this output may not exhibit a monotonic fall time and may even oscillate briefly while power is being restored to the protected device and the decou- pling capacitance is charged. loading on the status output should be minimized because this signal is used inter- nally by the 5102alp. it is recommended that load current not exceed 2 ma and load capacitance be kept will below 1000 pf. 7. when hold goes low, the analog sample is captured immediately. to start conversion, hold must be latched by a falling edge of clkin. conversion will begin on the next rising edge of clkin after hold is latched. 8. only valid for trk1 , trk2 falling when sclk is low. if sclk is high when trk1 , trk2 falls, then sdata is valid t dss time after the next falling sclk. t able 5. 5102alp d igital c haracteristics (t a = t min to t ma x; va+, vd+ = 5v 10%; va-, vd- = -5v 10%) p arameter s ymbol m in t yp m ax u nit calibration memory retention power supply voltage va+ & vd+ 1 1. va- and vd- can be any value from zero to -5v for memory retention. neither va- or vd- should be allowed to go positive. ain1, ain2 or v ref must not be greater than va+ or vd+. this parameter is guaranteed by characterization. v mr 2.0----v high-level input voltage v ih 2.0----v low-level input voltage v il -- -- 0.8 v high-level output voltage 2 2. i out = -100 a. this specification guarantees ttl compatibility (v oh = 2.4v @ i out = -40 a. v oh (vd+) -1.0 -- -- v low-level output voltage - i out = 1.6 ma v ol -- -- 0.4 v input leakage current i in -- -- 10 a digital output pin capacitance c out -- 9 -- pf
m e m o r y 7 01.17.05 r ev 3 all data sheets are subject to change without notice ?2005 maxwell technologies inc. all rights reserved. 5102alp 16-bit, 20 khz a/d converter 5102alp lpt tm b lock d iagram l atch - up p rotection c ircuit (lpt) p in d escription p in p in n ame f unction 18 lptbit the lpt circuit will crowbar the power supplies to the sei5102alprp for as long as a logi- cal high is applied. used to verify operation of the lpt. normally a logical low or ground is applied to this input. 26 -lptv negative power supply. va- and vd- are connected and can be measured on this pin. nor- mally -5v. 27 +lptv positive power supply. va+ and vd+ are connected and can be measured on this pin. nor- mally +5v. 5102a crowbar switch current sense timer control logic switch current sense ain 1 ain 2 vref +vdig +vana -vdig -vana +lptv -lptv lptbit lptstatus
m e m o r y 8 01.17.05 r ev 3 all data sheets are subject to change without notice ?2005 maxwell technologies inc. all rights reserved. 5102alp 16-bit, 20 khz a/d converter . f igure 1. r eset and c alibration t iming f igure 2. c ontrol o utput t iming f igure 3. c hannel s election t iming 39 lpt- sta- tus a 0 to 5v square-wave will output during a latch condition. normally low. l atch - up p rotection c ircuit (lpt) p in d escription p in p in n ame f unction
m e m o r y 9 01.17.05 r ev 3 all data sheets are subject to change without notice ?2005 maxwell technologies inc. all rights reserved. 5102alp 16-bit, 20 khz a/d converter f igure 4. s tart c onversion t iming f igure 5. s erial d ata t iming f igure 6. d ata t ransmission t iming
m e m o r y 10 01.17.05 r ev 3 all data sheets are subject to change without notice ?2005 maxwell technologies inc. all rights reserved. 5102alp 16-bit, 20 khz a/d converter f igure 7. b ypass c ircuit note: 1. cap must be connected to the device for proper operation. 4.7 f analog side. 1 f digital side. 2. unused logic inputs should be tied to +vd or dgnd. f igure 8. p ower - up r eset c ircuit 144 23 22 +vdig dgnd -vdig rst clkin xout stby dgnd +vdig trk1 trk2 crs/ fin ssh / sd l hold ch1/ 2 sclk + lptbi t nc -vdig -vdig dgnd +vdig +vanlog agnd -vanlog -lptv +lptv sd a ta code bp/ up outmod ain1 vref refbu f agnd -vanlog ain2 +vanlog lptstatus sckm od sleep -vanlog agnd +vanlog + + + + 1 f 1 f 4.7 f 4.7 f +vd rst 1n4148 +5v r c
m e m o r y 11 01.17.05 r ev 3 all data sheets are subject to change without notice ?2005 maxwell technologies inc. all rights reserved. 5102alp 16-bit, 20 khz a/d converter f44 note: all dimensions in inches 44 p in frp s ymbol d imension m in n om m ax a 0.256 0.282 0.308 b 0.014 0.017 0.020 c 0.009 0.010 0.012 d 1.089 1.100 1.111 e 0.564 0.570 0.576 e1 -- -- 0.600 e2 0.410 0.430 0.450 e3 0.044 0.070 -- e 0.050 bsc l 0.455 0.465 0.475 q 0.022 0.027 0.032 s1 0.005 -- -- n44
m e m o r y 12 01.17.05 r ev 3 all data sheets are subject to change without notice ?2005 maxwell technologies inc. all rights reserved. 5102alp 16-bit, 20 khz a/d converter important notice: these data sheets are created using the chip manufacturers published specifications. maxwell technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. the specifications presented within these data sheets represent the latest and most accurate information available to date. however, these specifications are subject to change without notice and maxwell technologies assumes no responsibility for the use of this information. maxwell technologies? products are not authorized for use as critical components in life support devices or systems without express written approval from maxwell technologies. any claim against maxwell technologiesinc. must be made within 90 days from the date of shipment from maxwell technologies. maxwell technologies? liability shall be limited to replacement of defective parts.
m e m o r y 13 01.17.05 r ev 3 all data sheets are subject to change without notice ?2005 maxwell technologies inc. all rights reserved. 5102alp 16-bit, 20 khz a/d converter product ordering options

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